1. Field of the Invention
The invention relates generally to a method of manufacturing semiconductor devices and, more particularly, to semiconductor devices and a method of manufacturing the same, in which a self-aligned electron trap film capable of securing a right and left-symmetrical type ONO film length can be formed.
2. Discussion of Related Art
In recent years, silicon-oxide-nitride-oxide-silicon (SONOS) type flash memory devices have been developed along with the development of flash memory devices. The SONOS type flash memory device is advantageous in that it can be easily fabricated and can be easily integrated with the peripheral region of such a device.
In the existing SONOS type flash memory device, an oxide-nitride-oxide (ONO) film (i.e., a dielectric film) exists entirely on a channel region. This thickens a gate oxide film formed on the ONO film. As a result, the SONOS type flash memory device has a high threshold voltage (Vt), and high power consumption and a high program voltage corresponding to the high threshold voltage.
Furthermore, electrons trapped at the silicon nitride film are moved in a horizontal direction in the silicon nitride film. Accordingly, the erase operation is not fully performed, and the erase rate is lengthened. On the other hand, as the program and erase operations are repeatedly performed, an initial threshold voltage (Vt) of an erased cell is increased. This can lower not only the cell current and the read speed, but also the data retention time.
To solve the problems, there has been proposed local SONOS type (i.e., electron trap film) flash memory devices in which the silicon nitride film is locally overlapped with the gate electrode. A gate formation method of the local SONOS type flash memory device will be described below with reference to FIGS. 1A to 1D.
Referring to FIG. 1A, an ONO film 11 (i.e., a dielectric film) is formed on a semiconductor substrate 10. The ONO film 11 is selectively etched by an etch process employing a mask.
Referring to FIG. 1B, a gate oxide film 12 and a polysilicon film 13 are formed on the entire structure.
Referring to FIG. 1C, a photoresist pattern 14 is formed on the entire structure. The photoresist pattern 14 may be misaligned.
Referring to FIG. 1D, the polysilicon film 13, the gate oxide film 12, and the ONO film 11 are etched using the photoresist pattern 14 as a mask, forming a gate 15.
If the gate is formed as described above, there occurs a phenomenon in which the length of the ONO film of a region A is asymmetrical to the length of the ONO film of a region B in the gate 15 due to the misaligned photoresist pattern 14, as shown in FIG. 1C. The length of the ONO film influences the erase rate, the erase efficiency, and the initial threshold voltage (Vt) of the flash memory device. If the length of the ONO film varies depending on a cell of a memory device, respective cells have different threshold voltages (Vt) and different erase rates.
Accordingly, problems arise because the uniformity within the entire wafer is lowered and the threshold voltage (Vt) is severely changed.